SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.

General Information

Status
Published
Publication Date
10-Oct-2023
Drafting Committee
Current Stage
PPUB - Publication issued
Start Date
08-Sep-2023
Completion Date
11-Oct-2023
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IEC 62530-2:2023 - SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual Released:11. 10. 2023
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IEC 62530-2
®
Edition 2.0 2023-10

IEEE Std 1800.2
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
IEC 62530-2:2023-10(en)  IEEE Std 1800.2-2020

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IEC 62530-2
®
Edition 2.0 2023-10
IEEE Std 1800.2™
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7516-0
 Warning! Make sure that you obtained this publication from an authorized distributor.
® Registered trademark of the International Electrotechnical Commission

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IEC 62530-2:2023 © IEC 2023
– i – IEEE Std 1800.2™-2020
Contents
1. Overview .12
1.1 Scope .12
1.2 Purpose .12
1.3 Word usage .12
1.4 Conventions used .13
2. Normative references .15
3. Definitions, acronyms, and abbreviations .15
3.1 Definitions .15
3.2 Acronyms and abbreviations .16
4. Universal Verification Methodology (UVM) class reference .17
5.
...

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